a. Field of the Invention
The present invention generally relates to semiconductor device testing, and more particularly, to semiconductor accelerated stress testing.
b. Background of Invention
During semiconductor accelerated stress testing and evaluation, when trying to compare two or more different stress results, variation within a sample population (e.g., single chip devices on the wafer or from differing wafers) can cause errors in interpreting the result. This variation may originate from multiple sources such as, but not limited to, wafer to wafer variability, wafer regionality, intentional process variation across the wafer, and any combination thereof.
Generally, defects within a wafer or between wafers may not be uniformly distributed. Thus, the interpreted results of the stress test may inadvertently depend to a certain degree on semiconductor wafer defects that may vary based on, for example, the location of the chip within a given wafer. The abovementioned affects may be exacerbated when yields per wafer are low, or when evaluating complex structures such as multichip modules, 3D stacked chips, etc., where chip parentage is more likely to differ.
For example, referring to FIG. 1A, in conventional stress testing, a number of sample chip devices, as denoted by cp, within a wafer 104 may be stressed as devices or after packaging (i.e., BAT device samples: Bonded Assembled and Tested device samples) under different stress conditions. For example, chip devices undergoing thermal stressing may be subjected to both a lower stress temperature condition and a higher stress temperature condition. As depicted, chip devices undergoing the lower stress temperature condition are identified by character A, while chip devices undergoing the higher stress temperature condition are indicated by character B.
Referring to FIG. 1B, the characteristics of wafer 104 may, for example, vary across the wafer 104, as indicated by 105a; vary according to regionality of the wafer 104, as indicated by 105b; or vary based on intentional process variations across the wafer 104, as indicated by 105c. 
Referring to FIGS. 1A and 1B, for example, chip 106 within wafer 104 may undergo stress condition A while chip 108 within wafer 104 may undergo stress condition B. However, due to variability across the wafer 104, as indicated at 110, the results of the applied stress to chips 106 and 108 may be influenced by the wafer variability as opposed to the response of the chip devices to applied stress conditions A and B. In another example, chip 106 within wafer 104 may undergo stress condition A while chip 108 within wafer 104 may undergo stress condition B. However, due to wafer variability at regions R1 and R2 of wafer 104, the results of the applied stress to chips 106 and 108 may be influenced by each chip 106, 108 being located in a different region R1, R2 rather than based on the response of the chip devices to applied stress conditions A and B. Similarly, wafer variability may be intentionally introduced at regions P1-P5 of wafer 104. This may occur as a result intentional process variations (e.g., regional doping) introduced at different regions P1-P5 across the wafer 104. For example, the applied stress conditions to chips 106 and 108 may be influenced by each chip 106, 108 being located in respective regions P5 and P4 rather than by the response of the chip devices to applied stress conditions A and B.
Thus, such variations may require an increased time and/or process overhead associated with selecting stress samples that are as homogenous as possible. Such challenges may become further exacerbated when the test samples (i.e., BAT device samples: Bonded Assembled and Tested device samples) include 3D stacked chip devices that may include semiconductor stacked layers having different wafer parentage.